Project

General

Profile

Download (1.94 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_12_ch_12_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
-- code from book
28

    
29
entity reg is
30
  generic ( width : positive );
31
  port ( d : in bit_vector(0 to width - 1);
32
         q : out bit_vector(0 to width - 1);
33
         -- . . . );
34
         -- not in book
35
         other_port : in bit := '0' );
36
  -- end not in book
37
end entity reg;
38

    
39
-- end code from book
40

    
41

    
42
architecture test of reg is
43
begin
44
  q <= d;
45
end architecture test;
46

    
47

    
48

    
49
entity ch_12_03 is
50

    
51
end entity ch_12_03;
52

    
53

    
54
----------------------------------------------------------------
55

    
56

    
57
architecture test of ch_12_03 is
58

    
59
  constant bus_size : positive := 16;
60

    
61
  -- code from book
62

    
63
  signal in_data, out_data : bit_vector(0 to bus_size - 1);
64
  -- . . .
65

    
66
  -- end code from book
67

    
68

    
69
begin
70

    
71
  -- code from book
72

    
73
  ok_reg : entity work.reg
74
    generic map ( width => bus_size )
75
    port map ( d => in_data,  q => out_data, -- . . . );
76
               -- not in book
77
               other_port => open );
78
  -- end not in book
79

    
80
  -- end code from book
81

    
82
end architecture test;
(280-280/372)