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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_12_ch_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book
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entity reg is
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  port ( d : in bit_vector;  q : out bit_vector;  -- . . . );
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  -- not in book
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  other_port : in bit := '0' );
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  -- end not in book
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end entity reg;
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-- end code from book
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architecture test of reg is
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begin
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  q <= d;
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end architecture test;
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entity ch_12_02 is
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end entity ch_12_02;
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----------------------------------------------------------------
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architecture test of ch_12_02 is
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  -- code from book
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  signal small_data : bit_vector(0 to 7);
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  signal large_data : bit_vector(0 to 15);
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  -- . . .
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  -- end code from book
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begin
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  -- code from book
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  problem_reg : entity work.reg
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    port map ( d => small_data,  q => large_data, -- . . . );
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               -- not in book
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               other_port => open );
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  -- end not in book
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  -- end code from book
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end architecture test;
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