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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_11_fg_11_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity bus_module is
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                 port ( synch : inout std_ulogic;  -- . . . );
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                        -- not in book
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                        other_port : in std_ulogic := 'U' );
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                 -- end not in book
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               end entity bus_module;
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--------------------------------------------------
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-- not in book
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               library ieee;  use ieee.std_logic_1164.all;
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               entity bus_based_system is
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               end entity bus_based_system;
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-- end not in book
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               architecture top_level of bus_based_system is
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                 signal synch_control : std_logic;
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                 -- . . .
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               begin
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                 synch_control_pull_up : synch_control <= 'H';
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                 bus_module_1 : entity work.bus_module(behavioral)
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                   port map ( synch => synch_control, -- . . . );
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                              -- not in book
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                              other_port => open );
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                 -- end not in book
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                 bus_module_2 : entity work.bus_module(behavioral)
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                   port map ( synch => synch_control, -- . . . );
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                              -- not in book
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                              other_port => open );
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                 -- end not in book
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                 -- . . .
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               end architecture top_level;
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