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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_11_fg_11_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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use work.words.all;
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entity cpu is
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port ( address : out uword; data : inout uword; -- . . . );
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-- not in book
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other_port : in X01Z := 'Z' );
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-- end not in book
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end entity cpu;
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-- not in book
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architecture behavioral of cpu is
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begin
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end architecture behavioral;
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-- end not in book
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--------------------------------------------------
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use work.words.all;
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entity memory is
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port ( address : in uword; data : inout uword; -- . . . );
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-- not in book
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other_port : in X01Z := 'Z' );
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-- end not in book
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end entity memory;
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-- not in book
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architecture behavioral of memory is
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begin
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end architecture behavioral;
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-- end not in book
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--------------------------------------------------
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-- not in book
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use work.words.all;
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entity ROM is
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port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
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end entity ROM;
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architecture behavioral of ROM is
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begin
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end architecture behavioral;
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entity computer_system is
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end entity computer_system;
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-- end not in book
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architecture top_level of computer_system is
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use work.words.all;
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signal address : uword;
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signal data : word;
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-- . . .
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begin
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the_cpu : entity work.cpu(behavioral)
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port map ( address, data, -- . . . );
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-- not in book
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open );
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-- end not in book
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the_memory : entity work.memory(behavioral)
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port map ( address, data, -- . . . );
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-- not in book
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open );
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-- end not in book
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-- . . .
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-- code from book (in text)
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-- boot_rom : entity work.ROM(behavioral)
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-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
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-- -- not in book
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-- other_port => open );
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-- -- end not in book
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-- end code from book
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end architecture top_level;
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