|
1
|
{
|
|
2
|
"DESIGN_FILE" : {
|
|
3
|
"design_units" : [{
|
|
4
|
"contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
|
|
5
|
"name" : ["IDENTIFIER", "reg"], "ports" : [{
|
|
6
|
"names" : [["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
|
|
7
|
"name" : ["SIMPLE_NAME", "std_ulogic"]}
|
|
8
|
}
|
|
9
|
, {
|
|
10
|
"names" : [["IDENTIFIER", "d"]], "mode" : ["in"], "typ" : {
|
|
11
|
"name" : ["SIMPLE_NAME", "std_ulogic_vector"]}
|
|
12
|
}
|
|
13
|
, {
|
|
14
|
"names" : [["IDENTIFIER", "q"]], "mode" : ["out"], "typ" : {
|
|
15
|
"name" : ["SIMPLE_NAME", "std_ulogic_vector"]}
|
|
16
|
}
|
|
17
|
], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
|
|
18
|
]}
|
|
19
|
]}
|
|
20
|
}
|