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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "reg"], "ports" : [{
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          "names" : [["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "d"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic_vector"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "q"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic_vector"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    ]}
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  }
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