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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version.
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_05.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity edge_triggered_Dff is
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port ( D : in bit; clk : in bit; clr : in bit;
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Q : out bit );
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end entity edge_triggered_Dff;
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architecture behavioral of edge_triggered_Dff is
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begin
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state_change : process (clk, clr) is
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begin
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if clr = '1' then
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Q <= '0' after 2 ns;
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elsif clk'event and clk = '1' then
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Q <= D after 2 ns;
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end if;
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end process state_change;
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end architecture behavioral;
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