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1
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{
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2
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"DESIGN_FILE" : {
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3
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"design_units" : [{
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4
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"contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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5
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"name" : ["IDENTIFIER", "struct"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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6
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"declaration" : ["SIGNAL_DECLARATION", {
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7
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"names" : [["IDENTIFIER", "int_clk"]], "typ" : {
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8
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"name" : ["SIMPLE_NAME", "bit"]}
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9
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}
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10
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]}
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11
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], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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12
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"name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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13
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"actual_designator" : ["SIMPLE_NAME", "d0"]}
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14
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, {
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15
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"actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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16
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, {
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17
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"actual_designator" : ["SIMPLE_NAME", "q0"]}
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18
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]}
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19
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], ["COMPONENT_INSTANTIATION_STATEMENT", {
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20
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"name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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21
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"actual_designator" : ["SIMPLE_NAME", "d1"]}
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22
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, {
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23
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"actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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24
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, {
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25
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"actual_designator" : ["SIMPLE_NAME", "q1"]}
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26
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]}
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27
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], ["COMPONENT_INSTANTIATION_STATEMENT", {
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28
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"name" : ["IDENTIFIER", "bit2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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29
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"actual_designator" : ["SIMPLE_NAME", "d2"]}
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30
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, {
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31
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"actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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32
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, {
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33
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"actual_designator" : ["SIMPLE_NAME", "q2"]}
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34
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]}
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35
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], ["COMPONENT_INSTANTIATION_STATEMENT", {
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36
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"name" : ["IDENTIFIER", "bit3"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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37
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"actual_designator" : ["SIMPLE_NAME", "d3"]}
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38
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, {
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39
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"actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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40
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, {
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41
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"actual_designator" : ["SIMPLE_NAME", "q3"]}
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42
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]}
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43
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], ["COMPONENT_INSTANTIATION_STATEMENT", {
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44
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"name" : ["IDENTIFIER", "gate"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "and2"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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45
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"actual_designator" : ["SIMPLE_NAME", "en"]}
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46
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, {
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47
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"actual_designator" : ["SIMPLE_NAME", "clk"]}
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48
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, {
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49
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"actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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50
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]}
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51
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]]}
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52
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]}
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53
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]}
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54
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}
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