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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_ap_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity bidir_buffer is
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                 port ( bidir : inout std_logic_vector;
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                        ena : in std_ulogic;
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                        going_out : in std_ulogic_vector;
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                        coming_in : out std_ulogic_vector );
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               end entity bidir_buffer;
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--------------------------------------------------
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               architecture behavior of bidir_buffer is
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-- code from book
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                 constant hi_impedance : std_logic_vector(bidir'range) := (others => 'Z');
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                 -- . . .
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-- end code from book
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               begin
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-- code from book
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                 bidir <= To_stdlogicvector(going_out) when ena = '1' else
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                          hi_impedance;
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                 coming_in <= To_stdulogicvector(bidir);
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-- end code from book
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               end architecture behavior;
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               entity ap_a_07 is
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               end entity ap_a_07;
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               library ieee;  use ieee.std_logic_1164.all;
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               architecture test of ap_a_07 is
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                 signal bidir : std_logic_vector(3 downto 0);
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                 signal going_out, coming_in : std_ulogic_vector(3 downto 0);
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                 signal ena : std_ulogic;
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               begin
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                 dut : entity work.bidir_buffer
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                   port map ( bidir, ena, going_out, coming_in );
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                 ena <= '0', '1' after 10 ns, '0' after 30 ns;
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                 going_out <= "0000", "1111" after 20 ns;
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                 bidir <= "ZZZZ", "0000" after 40 ns, "1111" after 50 ns, "ZZZZ" after 60 ns;
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               end architecture test;
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