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library ieee;
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use ieee.std_logic_1164.all;
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library alib;
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entity tb4 is
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end;
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architecture arch of tb4 is
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    signal a, b :  std_logic := '0';
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    component acomp is
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        port (x: in std_ulogic; y: out std_ulogic);
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    end component;
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begin
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    ainst: acomp
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        port map (a, b);
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    process is
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    begin
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        a <= '0';
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        wait for 1 ns;
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        assert b = '0' report "component is missing" severity failure;
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        a <= '1';
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        wait for 1 ns;
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        assert b = '1' report "component is missing" severity failure;
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        wait;
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  end process;
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end architecture;
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