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library ieee;
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use ieee.std_logic_1164.all;
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entity e1 is
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port(
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r1: in real;
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slv1: in std_logic_vector(7 downto 0);
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sl1: in std_logic
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);
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end;
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architecture a of e1 is
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begin
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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entity e2 is
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begin
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end;
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architecture a of e2 is
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constant r2: integer := 10e6;
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signal slv2: std_logic_vector(7 downto 0);
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signal sl2: std_logic;
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begin
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tx: entity work.e1
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port map(
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r1 => real(r2_wrong),
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slv1 => slv2,
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sl1 => sl2
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);
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end;
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