1

library ieee;

2

use ieee.std_logic_1164.all;

3


4

library ieee;

5

use ieee.numeric_std.all;

6


7

entity shr_141 is

8

port (

9

output : out std_logic_vector(31 downto 0);

10

input : in std_logic_vector(31 downto 0);

11

shift : in std_logic_vector(5 downto 0);

12

padding : in std_logic

13

);

14

end shr_141;

15


16

architecture augh of shr_141 is

17


18

signal tmp_padding : std_logic;

19

signal tmp_result : std_logic_vector(32 downto 0);

20


21

 Little utility functions to make VHDL syntactically correct

22

 with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.

23

 This happens when accessing arrays with <= 2 cells, for example.

24


25

function to_integer(B: std_logic) return integer is

26

variable V: std_logic_vector(0 to 0);

27

begin

28

V(0) := B;

29

return to_integer(unsigned(V));

30

end;

31


32

function to_integer(V: std_logic_vector) return integer is

33

begin

34

return to_integer(unsigned(V));

35

end;

36


37

begin

38


39

 Temporary signals

40

tmp_padding <= padding;

41

tmp_result <= std_logic_vector(shift_right( unsigned(padding & input), to_integer(shift) ));

42


43

 The output

44

output <= tmp_result(31 downto 0);

45


46

end architecture;
