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library ieee;

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use ieee.std_logic_1164.all;

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library ieee;

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use ieee.numeric_std.all;

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entity add_393 is

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port (

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result : out std_logic_vector(31 downto 0);

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in_a : in std_logic_vector(31 downto 0);

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in_b : in std_logic_vector(31 downto 0)

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);

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end add_393;

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architecture augh of add_393 is

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signal carry_inA : std_logic_vector(33 downto 0);

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signal carry_inB : std_logic_vector(33 downto 0);

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signal carry_res : std_logic_vector(33 downto 0);

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begin

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 To handle the CI input, the operation is '1' + CI

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 If CI is not present, the operation is '1' + '0'

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carry_inA <= '0' & in_a & '1';

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carry_inB <= '0' & in_b & '0';

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 Compute the result

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carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));

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 Set the outputs

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result <= carry_res(32 downto 1);

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end architecture;
