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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity shl_211 is
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port (
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output : out std_logic_vector(31 downto 0);
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input : in std_logic_vector(31 downto 0);
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shift : in std_logic_vector(5 downto 0);
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padding : in std_logic
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);
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end shl_211;
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architecture augh of shl_211 is
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signal tmp_padding : std_logic;
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signal tmp_result : std_logic_vector(32 downto 0);
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-- Little utility functions to make VHDL syntactically correct
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-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
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-- This happens when accessing arrays with <= 2 cells, for example.
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function to_integer(B: std_logic) return integer is
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variable V: std_logic_vector(0 to 0);
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begin
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V(0) := B;
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return to_integer(unsigned(V));
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end;
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function to_integer(V: std_logic_vector) return integer is
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begin
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return to_integer(unsigned(V));
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end;
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begin
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-- Temporary signals
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tmp_padding <= padding;
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tmp_result <= std_logic_vector(shift_left( unsigned(input & padding), to_integer(shift) ));
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-- The output
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output <= tmp_result(32 downto 1);
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end architecture;
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