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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity izigzag_index is
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port (
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clk : in std_logic;
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ra0_addr : in std_logic_vector(5 downto 0);
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ra0_data : out std_logic_vector(5 downto 0)
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);
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end izigzag_index;
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architecture augh of izigzag_index is
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-- Embedded RAM
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type ram_type is array (0 to 63) of std_logic_vector(5 downto 0);
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signal ram : ram_type := (
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"000000", "000001", "001000", "010000", "001001", "000010", "000011", "001010", "010001", "011000", "100000", "011001",
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"010010", "001011", "000100", "000101", "001100", "010011", "011010", "100001", "101000", "110000", "101001", "100010",
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"011011", "010100", "001101", "000110", "000111", "001110", "010101", "011100", "100011", "101010", "110001", "111000",
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"111001", "110010", "101011", "100100", "011101", "010110", "001111", "010111", "011110", "100101", "101100", "110011",
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"111010", "111011", "110100", "101101", "100110", "011111", "100111", "101110", "110101", "111100", "111101", "110110",
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"101111", "110111", "111110", "111111"
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);
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-- Little utility functions to make VHDL syntactically correct
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-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
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-- This happens when accessing arrays with <= 2 cells, for example.
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function to_integer(B: std_logic) return integer is
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variable V: std_logic_vector(0 to 0);
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begin
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V(0) := B;
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return to_integer(unsigned(V));
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end;
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function to_integer(V: std_logic_vector) return integer is
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begin
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return to_integer(unsigned(V));
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end;
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begin
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-- The component is a ROM.
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-- There is no Write side.
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-- The Read side (the outputs)
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ra0_data <= ram( to_integer(ra0_addr) );
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end architecture;
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