|
1
|
library ieee;
|
|
2
|
use ieee.std_logic_1164.all;
|
|
3
|
|
|
4
|
|
|
5
|
library ieee;
|
|
6
|
use ieee.numeric_std.all;
|
|
7
|
|
|
8
|
entity extend_mask is
|
|
9
|
port (
|
|
10
|
clk : in std_logic;
|
|
11
|
ra0_addr : in std_logic_vector(4 downto 0);
|
|
12
|
ra0_data : out std_logic_vector(20 downto 0)
|
|
13
|
);
|
|
14
|
end extend_mask;
|
|
15
|
architecture augh of extend_mask is
|
|
16
|
|
|
17
|
-- Embedded RAM
|
|
18
|
|
|
19
|
type ram_type is array (0 to 19) of std_logic_vector(20 downto 0);
|
|
20
|
signal ram : ram_type := (
|
|
21
|
"111111111111111111110", "111111111111111111100", "111111111111111111000", "111111111111111110000",
|
|
22
|
"111111111111111100000", "111111111111111000000", "111111111111110000000", "111111111111100000000",
|
|
23
|
"111111111111000000000", "111111111110000000000", "111111111100000000000", "111111111000000000000",
|
|
24
|
"111111110000000000000", "111111100000000000000", "111111000000000000000", "111110000000000000000",
|
|
25
|
"111100000000000000000", "111000000000000000000", "110000000000000000000", "100000000000000000000"
|
|
26
|
);
|
|
27
|
|
|
28
|
|
|
29
|
-- Little utility functions to make VHDL syntactically correct
|
|
30
|
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
|
|
31
|
-- This happens when accessing arrays with <= 2 cells, for example.
|
|
32
|
|
|
33
|
function to_integer(B: std_logic) return integer is
|
|
34
|
variable V: std_logic_vector(0 to 0);
|
|
35
|
begin
|
|
36
|
V(0) := B;
|
|
37
|
return to_integer(unsigned(V));
|
|
38
|
end;
|
|
39
|
|
|
40
|
function to_integer(V: std_logic_vector) return integer is
|
|
41
|
begin
|
|
42
|
return to_integer(unsigned(V));
|
|
43
|
end;
|
|
44
|
|
|
45
|
begin
|
|
46
|
|
|
47
|
-- The component is a ROM.
|
|
48
|
-- There is no Write side.
|
|
49
|
|
|
50
|
-- The Read side (the outputs)
|
|
51
|
|
|
52
|
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 20 else (others => '-');
|
|
53
|
|
|
54
|
end architecture;
|