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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity bit_set_mask is
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port (
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clk : in std_logic;
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ra0_addr : in std_logic_vector(4 downto 0);
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ra0_data : out std_logic_vector(31 downto 0)
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);
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end bit_set_mask;
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architecture augh of bit_set_mask is
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-- Embedded RAM
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type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
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signal ram : ram_type := (
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"00000000000000000000000000000001", "00000000000000000000000000000010", "00000000000000000000000000000100",
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"00000000000000000000000000001000", "00000000000000000000000000010000", "00000000000000000000000000100000",
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"00000000000000000000000001000000", "00000000000000000000000010000000", "00000000000000000000000100000000",
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"00000000000000000000001000000000", "00000000000000000000010000000000", "00000000000000000000100000000000",
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"00000000000000000001000000000000", "00000000000000000010000000000000", "00000000000000000100000000000000",
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"00000000000000001000000000000000", "00000000000000010000000000000000", "00000000000000100000000000000000",
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"00000000000001000000000000000000", "00000000000010000000000000000000", "00000000000100000000000000000000",
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"00000000001000000000000000000000", "00000000010000000000000000000000", "00000000100000000000000000000000",
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"00000001000000000000000000000000", "00000010000000000000000000000000", "00000100000000000000000000000000",
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"00001000000000000000000000000000", "00010000000000000000000000000000", "00100000000000000000000000000000",
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"01000000000000000000000000000000", "10000000000000000000000000000000"
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);
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-- Little utility functions to make VHDL syntactically correct
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-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
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-- This happens when accessing arrays with <= 2 cells, for example.
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function to_integer(B: std_logic) return integer is
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variable V: std_logic_vector(0 to 0);
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begin
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V(0) := B;
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return to_integer(unsigned(V));
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end;
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function to_integer(V: std_logic_vector) return integer is
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begin
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return to_integer(unsigned(V));
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end;
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begin
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-- The component is a ROM.
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-- There is no Write side.
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-- The Read side (the outputs)
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ra0_data <= ram( to_integer(ra0_addr) );
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end architecture;
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