1
|
-------------------------------------------------------------------------------------------------
|
2
|
-- Company : CNES
|
3
|
-- Author : Mickael Carl (CNES)
|
4
|
-- Copyright : Copyright (c) CNES.
|
5
|
-- Licensing : GNU GPLv3
|
6
|
-------------------------------------------------------------------------------------------------
|
7
|
-- Version : V1
|
8
|
-- Version history :
|
9
|
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
|
10
|
-------------------------------------------------------------------------------------------------
|
11
|
-- File name : CNE_05100_good.vhd
|
12
|
-- File Creation date : 2015-04-14
|
13
|
-- Project name : VHDL Handbook CNES Edition
|
14
|
-------------------------------------------------------------------------------------------------
|
15
|
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
|
16
|
-------------------------------------------------------------------------------------------------
|
17
|
-- Description : Handbook example: Multiplexor single process based: good example
|
18
|
--
|
19
|
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
|
20
|
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
|
21
|
-- It is provided as is, without any warranty.
|
22
|
-- This example is compliant with the Handbook version 1.
|
23
|
--
|
24
|
-------------------------------------------------------------------------------------------------
|
25
|
-- Naming conventions:
|
26
|
--
|
27
|
-- i_Port: Input entity port
|
28
|
-- o_Port: Output entity port
|
29
|
-- b_Port: Bidirectional entity port
|
30
|
-- g_My_Generic: Generic entity port
|
31
|
--
|
32
|
-- c_My_Constant: Constant definition
|
33
|
-- t_My_Type: Custom type definition
|
34
|
--
|
35
|
-- My_Signal_n: Active low signal
|
36
|
-- v_My_Variable: Variable
|
37
|
-- sm_My_Signal: FSM signal
|
38
|
-- pkg_Param: Element Param coming from a package
|
39
|
--
|
40
|
-- My_Signal_re: Rising edge detection of My_Signal
|
41
|
-- My_Signal_fe: Falling edge detection of My_Signal
|
42
|
-- My_Signal_rX: X times registered My_Signal signal
|
43
|
--
|
44
|
-- P_Process_Name: Process
|
45
|
--
|
46
|
-------------------------------------------------------------------------------------------------
|
47
|
|
48
|
library IEEE;
|
49
|
use IEEE.std_logic_1164.all;
|
50
|
use IEEE.numeric_std.all;
|
51
|
|
52
|
entity CNE_05100_good is
|
53
|
port (
|
54
|
i_A : in std_logic; -- First Mux input
|
55
|
i_B : in std_logic; -- Second Mux input
|
56
|
i_S : in std_logic; -- Mux select
|
57
|
o_O : out std_logic -- Mux output
|
58
|
);
|
59
|
end CNE_05100_good;
|
60
|
|
61
|
architecture Behavioral of CNE_05100_good is
|
62
|
signal O : std_logic; -- Mux output
|
63
|
begin
|
64
|
--CODE
|
65
|
-- Mux asynchronous process
|
66
|
P_Mux:process(i_S, i_A, i_B)
|
67
|
begin
|
68
|
if (i_S='1') then
|
69
|
O <= i_B;
|
70
|
else
|
71
|
O <= i_A;
|
72
|
end if;
|
73
|
end process;
|
74
|
|
75
|
o_O <= O;
|
76
|
--CODE
|
77
|
end Behavioral;
|