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1 3fd18385 Arnaud Dieumegard
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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1744.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c09s05b00x00p03n01i01744ent IS
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  port   (parallel_in    : bit_vector (7 downto 0);
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          clock      : bit;
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          serial_out   : out bit);
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END c09s05b00x00p03n01i01744ent;
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ARCHITECTURE c09s05b00x00p03n01i01744arch OF c09s05b00x00p03n01i01744ent IS
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  constant    bit_time    : time    := 1 ns;
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  signal       GUARD      : boolean:= TRUE;
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BEGIN
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  serial_out <= guarded transport    -- No_failure_here
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                parallel_in(7) after 1*bit_time,
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                parallel_in(6) after 2*bit_time,
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                parallel_in(5) after 3*bit_time,
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                parallel_in(4) after 4*bit_time,
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                parallel_in(3) after 5*bit_time,
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                parallel_in(2) after 6*bit_time,
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                parallel_in(1) after 7*bit_time,
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                parallel_in(0) after 8*bit_time,
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                '0' after 9*bit_time;
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  PROCESS
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  BEGIN
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    assert FALSE 
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      report "***PASSED TEST: c09s05b00x00p03n01i01744" 
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      severity NOTE;
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    wait;
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  END PROCESS;
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END c09s05b00x00p03n01i01744arch;