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1 3fd18385 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_05_06 is
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end entity ch_05_06;
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----------------------------------------------------------------
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architecture test of ch_05_06 is
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  signal y : bit := '0';
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  signal or_a_b : bit := '0';
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  signal clk : bit := '0';
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begin
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  process_05_3_a : process is
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  begin
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    -- code from book:
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    y <= not or_a_b after 5 ns;
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    -- end of code from book
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    wait on or_a_b;
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  end process process_05_3_a;
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  stimulus_05_3_a : process is
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  begin
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    or_a_b <= '1' after 20 ns,
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              '0' after 40 ns;
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    wait;
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  end process stimulus_05_3_a;
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  process_05_3_b : process is
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                             constant T_pw : delay_length := 10 ns;
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  begin
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    -- code from book:
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    clk <= '1' after T_pw, '0' after 2*T_pw;
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    -- end of code from book
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    wait for 2*T_pw;
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  end process process_05_3_b;
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end architecture test;