CristalCaveGem » LustreC » Lustrec-Tests

library IEEE;

use IEEE.std_logic_1164.all;

entity centisecond_timer is

   generic

   (

   ---- For implementation:

   -- g_clock_cycle_per_centisecond: natural := 500000

   ---- For testing, we recommend using:

      g_clock_cycle_per_centisecond: natural := 8

   );

   port

   (

      i_clock:           in std_logic; -- System clock.

      i_reset:           in std_logic; -- System reset.

      i_raz:             in std_logic; -- User triggered raz.

      i_enable:          in std_logic; -- Time is passing.

      o_new_centisecond: out std_logic -- Centisecond pulse.

   );

end centisecond_timer;

architecture behavioral of centisecond_timer is

   -- Having a range of 0 to (CLOCK_CYCLE_PER_CENTISECOND - 1) seems less

   -- readable, so we start at 1.

   signal timer: natural range 1 to g_clock_cycle_per_centisecond;

begin

   P_TIME_COUNTER: process (i_clock, i_reset)

   begin

      if (i_reset = '1')

      then

         timer <= 1;

      else

         if (rising_edge(i_clock))

         then

            if (i_raz = '1')

            then

               -- Reset has been requested.

               timer <= 1;

            else

               -- No reset has been requested.

               if

               (

                  (i_enable = '0')

                  or (timer >= g_clock_cycle_per_centisecond)

               )

               then

                  timer <= 1;

               elsif (i_enable = '1')

               then

                  timer <= (timer + 1);

               end if;

            end if;

         end if;

      end if;

   end process;

   o_new_centisecond <=

      i_enable

      when (timer >= g_clock_cycle_per_centisecond)

      else '0'

   ;

end;