|
1
|
library ieee;
|
|
2
|
use ieee.std_logic_1164.all;
|
|
3
|
|
|
4
|
entity counter is
|
|
5
|
port (x : in boolean;
|
|
6
|
clk : in std_logic;
|
|
7
|
o : out boolean);
|
|
8
|
end counter;
|
|
9
|
|
|
10
|
architecture greycounter of counter is
|
|
11
|
signal a,b: boolean := false;
|
|
12
|
begin
|
|
13
|
p: process (clk)
|
|
14
|
begin
|
|
15
|
if (clk'event and clk = '1') then
|
|
16
|
a <= not b;
|
|
17
|
b <= a;
|
|
18
|
end if;
|
|
19
|
end process;
|
|
20
|
o <= a and b;
|
|
21
|
end;
|
|
22
|
|
|
23
|
architecture intloopcounter of counter is
|
|
24
|
signal t: integer := 0;
|
|
25
|
begin
|
|
26
|
p : process (clk)
|
|
27
|
begin
|
|
28
|
if (clk'event and clk = '1') then
|
|
29
|
if t = 3 then
|
|
30
|
t <= 0;
|
|
31
|
else
|
|
32
|
t <= t + 1;
|
|
33
|
end if;
|
|
34
|
end if;
|
|
35
|
end process p;
|
|
36
|
o <= t = 2;
|
|
37
|
end;
|
|
38
|
|
|
39
|
library ieee;
|
|
40
|
use ieee.std_logic_1164.all;
|
|
41
|
|
|
42
|
entity top is
|
|
43
|
port (x : in boolean;
|
|
44
|
clk : in std_logic;
|
|
45
|
ok : out boolean);
|
|
46
|
end top;
|
|
47
|
|
|
48
|
-- Ensures ok;
|
|
49
|
architecture top_behav of top is
|
|
50
|
signal b,d: boolean;
|
|
51
|
begin
|
|
52
|
gcount: entity work.counter(greycounter) port map (x,clk,b);
|
|
53
|
icount: entity work.counter(intloopcounter) port map (x,clk,d);
|
|
54
|
ok <= b = d;
|
|
55
|
end;
|