CristalCaveGem » LustreC » Lustrec-Tests

library ieee;

use ieee.std_logic_1164.all;

entity counter is

  port (x   : in  boolean;

        clk : in  std_logic;

        o   : out boolean);

end counter;

architecture greycounter of counter is

  signal a,b: boolean := false;

begin

  p: process (clk)

  begin

    if (clk'event and clk = '1') then

      a <= not b;

      b <= a;

    end if;

  end process;

  o <= a and b;

end;

architecture intloopcounter of counter is

  signal t: integer := 0;

begin

  p : process (clk)

  begin

    if (clk'event and clk = '1') then

      if t = 3 then 

        t <= 0;

      else

        t <= t + 1;

      end if;

    end if;

  end process p;

  o <= t = 2;

end;

library ieee;

use ieee.std_logic_1164.all;

entity top is

  port (x     : in  boolean;

        clk   : in  std_logic;

        ok    : out boolean);

end top;

-- Ensures ok;

architecture top_behav of top is

  signal b,d: boolean;

begin

  gcount: entity work.counter(greycounter) port map (x,clk,b);

  icount: entity work.counter(intloopcounter) port map (x,clk,d);

  ok <= b = d;

end;