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Revision 26dc0008

Added by Arnaud Dieumegard over 3 years ago

Added example from some courses

View differences:

vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.json
1
{
2
  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
5
        "name" : ["IDENTIFIER", "reg4"], "ports" : [{
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          "names" : [["IDENTIFIER", "d0"], ["IDENTIFIER", "d1"], ["IDENTIFIER", "d2"], ["IDENTIFIER", "d3"], ["IDENTIFIER", "en"], ["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
7
            "name" : ["SIMPLE_NAME", "bit"]}
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          }
9
        , {
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          "names" : [["IDENTIFIER", "q0"], ["IDENTIFIER", "q1"], ["IDENTIFIER", "q2"], ["IDENTIFIER", "q3"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
14
      ]}
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    , {
16
      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
17
        "name" : ["IDENTIFIER", "behav"], "entity" : ["IDENTIFIER", "reg4"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
18
          "id" : ["IDENTIFIER", "storage"], "PROCESS_DECLARATIVE_PART" : [{
19
            "declaration" : ["VARIABLE_DECLARATION", {
20
              "names" : [["IDENTIFIER", "stored_d0"], ["IDENTIFIER", "stored_d1"], ["IDENTIFIER", "stored_d2"], ["IDENTIFIER", "stored_d3"]], "typ" : {
21
                "name" : ["SIMPLE_NAME", "bit"]}
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              }
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            ]}
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          ], "active_sigs" : [["SIMPLE_NAME", "d0"], ["SIMPLE_NAME", "d1"], ["SIMPLE_NAME", "d2"], ["SIMPLE_NAME", "d3"], ["SIMPLE_NAME", "en"], ["SIMPLE_NAME", "clk"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
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            "if_cases" : [{
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              "if_cond" : ["EXPRESSION", {
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                "id" : "and", "args" : [["EXPRESSION", {
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                  "id" : "=", "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "en"]]]}
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                      ]]}
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                    ]]}
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                  ], ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CONSTANT_VALUE", {
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                          "value" : ["CST_LITERAL", "'1'"]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ], ["EXPRESSION", {
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                  "id" : "=", "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "clk"]]]}
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                      ]]}
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                    ]]}
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                  ], ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CONSTANT_VALUE", {
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                          "value" : ["CST_LITERAL", "'1'"]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "if_block" : [["VARIABLE_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "stored_d0"], "rhs" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d0"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]}
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              ], ["VARIABLE_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "stored_d1"], "rhs" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d1"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]}
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              ], ["VARIABLE_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "stored_d2"], "rhs" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d2"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]}
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              ], ["VARIABLE_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "stored_d3"], "rhs" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d3"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          ], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "q0"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "stored_d0"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "delay" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "stored_d1"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "delay" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "q2"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "stored_d2"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "delay" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "q3"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "stored_d3"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "delay" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"]]}
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        ]]}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "d_latch"], "ports" : [{
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          "names" : [["IDENTIFIER", "d"], ["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "q"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "basic"], "entity" : ["IDENTIFIER", "d_latch"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
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          "id" : ["IDENTIFIER", "latch_behavior"], "active_sigs" : [["SIMPLE_NAME", "clk"], ["SIMPLE_NAME", "d"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
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            "if_cases" : [{
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              "if_cond" : ["EXPRESSION", {
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                "id" : "=", "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "clk"]]]}
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                    ]]}
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                  ]]}
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                ], ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'1'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "q"], "rhs" : [{
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                  "value" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["CALL", ["SIMPLE_NAME", "d"]]]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ], "delay" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["CONSTANT_VALUE", {
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                            "value" : ["CST_LITERAL", "2"], "unit_name" : ["SIMPLE_NAME", "ns"]}
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                          ]]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]}
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              ]]}
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            ]}
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          ], ["WAIT_STATEMENT"]]}
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        ]]}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "and2"], "ports" : [{
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          "names" : [["IDENTIFIER", "a"], ["IDENTIFIER", "b"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "y"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "basic"], "entity" : ["IDENTIFIER", "and2"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
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          "id" : ["IDENTIFIER", "and2_behavior"], "active_sigs" : [["SIMPLE_NAME", "a"], ["SIMPLE_NAME", "b"]], "PROCESS_STATEMENT_PART" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "y"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "id" : "and", "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "a"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ], ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "b"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "delay" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "2"], "unit_name" : ["SIMPLE_NAME", "ns"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"]]}
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        ]]}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "struct"], "entity" : ["IDENTIFIER", "ref4"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "int_clk"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "d0"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "q0"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "d1"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "q1"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "d2"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "q2"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit3"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "d3"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "q3"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "gate"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "and2"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "en"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
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          ]}
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        ]]}
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      ]}
353
    ]}
354
  }
vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.vhd
1
--- Extracted from https://www.ee.ryerson.ca/~courses/coe608/lectures/VHDL-intro.pdf p14-15
2

  
3
-- main entity
4
entity reg4 is
5
  port (d0, d1, d2, d3, en, clk: in bit; 
6
        q0, q1, q2, q3 : out bit );
7
end entity reg4;
8

  
9
-- main archi
10
architecture behav of reg4 is
11
  begin
12
    storage: process (d0, d1, d2, d3, en, clk) is
13
      variable stored_d0, stored_d1, stored_d2, stored_d3: bit;
14
    begin
15
      if en = '1' and clk = '1' then
16
        stored_d0 := d0;
17
        stored_d1 := d1;
18
        stored_d2 := d2;
19
        stored_d3 := d3;
20
      end if;
21
      q0 <= stored_d0 after 5 ns;
22
      q1 <= stored_d1 after 5 ns;
23
      q2 <= stored_d2 after 5 ns;
24
      q3 <= stored_d3 after 5 ns;
25
      wait;
26
    end process storage;
27
end architecture behav;
28

  
29
-- D-latch
30
entity d_latch is
31
  port (d, clk: in bit; q: out bit);
32
end entity d_latch;
33

  
34
architecture basic of d_latch is
35
begin
36
  latch_behavior : process (clk, d) is
37
  begin
38
    if clk = '1' then
39
      q <= d after 2ns;
40
    end if;
41
    wait;
42
  end process latch_behavior;
43
end architecture basic;
44

  
45
-- and-gate
46
entity and2 is
47
  port (a, b: in bit; y: out bit);
48
end entity and2;
49

  
50
architecture basic of and2 is
51
  begin
52
  and2_behavior: process (a,b) is
53
  begin
54
    y <= a and b after 2ns;
55
    wait;
56
  end process and2_behavior;
57
gnd architecture basic;
58

  
59
-- Main archi
60
architecture struct of reg4 is
61
  signal int_clk: bit;
62
  begin
63
    bit0: entity work.d_latch(basic)
64
    port map (d0, int_clk, q0);
65
    bit1: entity work.d_latch(basic)
66
    port map (d1, int_clk, q1);
67
    bit2: entity work.d_latch(basic)
68
    port map (d2, int_clk, q2);
69
    bit3: entity work.d_latch(basic)
70
    port map (d3, int_clk, q3);
71
    gate: entity work.and2(basic)
72
    port map (en, clk, int_clk);
73
end architecture struct;
74

  
75
-- Elaborated archi
76
-- architecture struct of ref4 is
77
--   signal int_clk: bit;
78
--   begin
79
--     bit0_latch_behavior : process (int_clk, d0) is
80
--     begin
81
--       if int_clk = '1' then
82
--         q0 <= d0 after 2ns;
83
--       end if;
84
--       wait;
85
--     end process bit0_latch_behavior;
86
--     bit1_latch_behavior : process (int_clk, d1) is
87
--     begin
88
--       if int_clk = '1' then
89
--         q1 <= d1 after 2ns;
90
--       end if;
91
--       wait;
92
--     end process bit1_latch_behavior;
93
--     bit2_latch_behavior : process (int_clk, d2) is
94
--     begin
95
--       if int_clk = '1' then
96
--         q2 <= d2 after 2ns;
97
--       end if;
98
--       wait;
99
--     end process bit2_latch_behavior;
100
--     bit3_latch_behavior : process (int_clk, d3) is
101
--     begin
102
--       if int_clk = '1' then
103
--         q3 <= d3 after 2ns;
104
--       end if;
105
--       wait;
106
--     end process bit3_latch_behavior;
107
--     gate_and2_behavior: process (en, clk) is
108
--     begin
109
--       int_clk <= en and clk after 2ns;
110
--       wait;
111
--     end process gate_and2_behavior;
112
-- end architecture struct;

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