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Revision 1c688dd0

Added by Arnaud Dieumegard over 3 years ago

Continue even if generation fails

View differences:

vhdl_json/Makefile
12 12
test: $(DSTS_VHD)	$(DSTS_MVHD)
13 13

  
14 14
%.json.vhd : %.json
15
	$(EXEC) $(OPTIONS) $(GEN_VHDL) $(OUTPUT) $@ $<
15
	-$(EXEC) $(OPTIONS) $(GEN_VHDL) $(OUTPUT) $@ $<
16 16

  
17 17
%.mvhd : %.json
18
	$(EXEC) $(OPTIONS) $(GEN_MINIVHDL) $(OUTPUT) $@ $<
18
	-$(EXEC) $(OPTIONS) $(GEN_MINIVHDL) $(OUTPUT) $@ $<
19 19

  
20 20
clean:
21 21
	@$(RM) -f $(DSTS)

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