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Bug #66 » SampleTime4.lus

Hamza Bourbouh, 05/31/2018 11:32 AM

 
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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (ToLustre.m)
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-- Time: 31-May-2018 11:24:41
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--external libraries
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node _make_clock(per: int; ph: int)
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returns( clk: bool );
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var cnt: int;
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let
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	cnt   = ((per - ph) -> (pre(cnt) + 1)) mod per ;
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	clk = if (cnt = 0) then true else false ;
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node int_to_int8 (x: int)
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returns(y:int);
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let
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	y= if x > 127 then -128 + rem_int_int((x - 127 - 1),256) 
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	else if x < -128 then 127 + rem_int_int((x - (-128) + 1),256) 
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	else x;
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node rem_int_int (x, y: int)
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returns(z:int);
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let
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	z = if y=0 then 0
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		else
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		 (x mod y) - (if (x mod y <> 0 and x <= 0) then (if y > 0 then y else -y) else 0);
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--Simulink code
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-- Original block name: SampleTime4/Subsystem1
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node Subsystem1_10_005 (In1_1: int;__time_step:real;_clk_2_0, _clk_4_0:bool clock;)
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 returns (Out1_1: int;
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Out2_1: int;);
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-- Contract In progress
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var RateTransition1_1: int;RateTransition2_1: int;RateTransition3_1: int;Sum_1: int;UnitDelay_1: int;UnitDelay1_1: int;
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let
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	RateTransition1_1 = Sum_1 when _clk_2_0;
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	RateTransition2_1 = merge _clk_2_0
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	 (true -> (0 -> pre UnitDelay_1))
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	 (false -> (0 -> pre RateTransition2_1) when false(_clk_2_0));
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	RateTransition3_1 = Sum_1 when _clk_4_0;
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	Sum_1 = int_to_int8(0 + In1_1 + RateTransition2_1);
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	UnitDelay_1 =  int_to_int8(0) -> pre( RateTransition1_1 ) ;
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	UnitDelay1_1 =  int_to_int8(0) -> pre( RateTransition3_1 ) ;
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	Out1_1 = UnitDelay_1;
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	Out2_1 = UnitDelay1_1;
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-- Original block name: SampleTime4
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node SampleTime4 (_virtual:bool;)
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 returns (Out1_1: int;
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Out2_1: int;);
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-- Contract In progress
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var Constant_1: int;RateTransition_1: int;RateTransition1_1: int;Subsystem1_1: int;
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	Subsystem1_2: int;
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	__time_step:real;
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	_clk_2_0, _clk_4_0:bool clock;
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let
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	_clk_4_0 = _make_clock(4, 0);
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	_clk_2_0 = _make_clock(2, 0);
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	__time_step = 0.0 -> pre __time_step + 1.000000000000000;
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	Constant_1 = 1;
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	RateTransition_1 = merge _clk_2_0
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	 (true -> (0 -> pre Subsystem1_1))
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	 (false -> (0 -> pre RateTransition_1) when false(_clk_2_0));
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	RateTransition1_1 = merge _clk_4_0
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	 (true -> (0 -> pre Subsystem1_2))
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	 (false -> (0 -> pre RateTransition1_1) when false(_clk_4_0));
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	(Subsystem1_1,
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	Subsystem1_2) = Subsystem1_10_005(Constant_1,
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		__time_step, _clk_2_0, _clk_4_0);
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	Out1_1 = RateTransition_1;
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	Out2_1 = RateTransition1_1;
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